In a pipelined processing environment, work arrives at a fixed rate. For example, in a network processor application, network packets may arrive every “n” ns. Each arriving packet requires access to information stored in memory (e.g., SRAM). Because the memory access speed is slower than the arrival rate, a pipeline is used to process the packets. The exit rate must match the arrival rate. Each packet is classified into a flow. Successively arriving packets may be from different flows, or from the same flow. In the case of the same flow, processing steps must be performed for each packet in strict arrival order.
In prior pipelined network processor implementations, data rates and memory access speeds for “same flow” packet processing are in a ratio such that the memory read access time is not greater than the packet arrival rate. Thus, the network processor cannot rely on a full pipeline rate without requiring faster memory access speeds.